_____________________________________________________________________________________________________________________________ _________________ dsc557 - 05 page 1 crystal - less ? four output pcie clock generator dsc 557 - 05 general description the dsc557 - 05 is a c rystal - less ? , four output pci express clock generator meeting gen1, gen2, and gen3 specifications . the clock generator uses proven silicon mems technology to provide excellent jitter and stability over a wide range of supply voltages and temperatures. by eliminating the external quartz crystal, mems clock generators significantly enhance reliability and accelerate product development, while meeting stringent clock performance criteria for a variety of communications, storage, and networking applications. dsc557 - 05 has a n output enable / disable feature allowing i t to disable all outputs when oe1 and oe2 are l ow. each output enable pin controls two banks of synchronous pcie clocks. see the oe function diagram for more detail. the device is available in a 20 pin qfn. additional output formats are in any combination of lvpecl, lvds, and hcsl. bl ock diagram * clk0+/ - , clk1+/ - , clk2 +/ - and clk3 +/ - are 100 mhz as per pcie s tandards. for other frequencies, please c ontact the factory. features ? meets pcie gen1, gen2 & g en3 specs ? available output formats: o hcsl, lvpecl, or lv ds o mixed outputs: lvpecl/hcsl/lvds ? wide temperature range o ext. industrial: - 40 to 105 c o industrial: - 40 to 85 c o ext. commercial: - 20 to 70 c ? supply range of 2.25 to 3.6 v ? low power consumption o 30% lower than competing devices ? excellent shock & vibration immunity o qualified to mil - std - 883 ? available footprints: o 20 qfn ? lead free & rohs compliant ? short lead time: 2 weeks applications ? communications/networking o ethernet o 1g, 10gbase - t/kr/lr/sr, and fcoe o routers and switches o gateways, voip, wireless aps o passive optical networks ? storage o san, nas, ssd, jbod ? embedded applications o industrial, medical, and avionics o security systems and office automation o digital signage, pos and others ? consumer electronics o smart tv, bluray, stb
_____________________________________________________________________________________________________________________________ _________________ dsc557 - 05 page 2 dsc557 - 0 5 crystal - less four output pcie clock g enerator s pecifications (unless specified otherwise: t=25 c , vdd =3.3v ) notes: 1. each v dd pin should be filtered with 0.01uf capacitor. 2. output is enabled if oe pin is floated or not connected. 3. t su is time to 100ppm stable output frequency after v dd is applied and outputs are enabled. 4. output waveform and connection diagram define the parameters. 5. period jitter includes crosstalk from adjacent output. 6. contact sales@discera.com for alternate output options (lvpecl, lvds, lvcmos). 7. contact sales@discera.com for alternative frequency options 8. jitter limits established by gen 1.1, gen 2.1, and gen 3.0 pcie standards. parameter condition min. typ. max. unit supply voltage 1 v dd 2.25 3.6 v supply current i dd en pin low C outputs are disabled 42 46 ma supply current 2 ( four hcsl outputs) i dd en pin high C outputs are enabled r l = 50 , f o1 =f o2 = f o3 = f o4 = 100 mhz 12 0 ma frequency stability f includes frequency variations due to initial tolerance, temp. and power supply voltage 100 ppm 50 startup time 3 t su t= 25c 5 ms input logic levels input logic hig h input logic low v ih v il 0.75 x v d d - - 0.25x v dd v output disable time 4 t da 5 ns output enable time t en 20 n s pull - up resistor 2 pull - up on oe pin 40 k hcsl outputs 6 parameter condition min. typ. max. unit output logic levels output logic high output logic low v oh v ol r l = 5 0 0.725 - - 0.1 v pk to pk output swing single - ended 750 mv output transition time 4 rise time fall time t r t f 20% to 80% r l = 5 0 , c l = 2pf 200 400 ps frequency f 0 single frequency 2.3 100 7 4 60 mhz output duty cycle sym differential 4 8 5 2 % period jitter 5 j per f o1 =f o2 = f o3 = f o4 = 1 00 mhz 2. 5 ps rms jitter, phase (common clock architecture) t j pcie gen 1.1 22.7 86.0 8 ps p - p j rms - cchf pcie gen 2.1, 1.5mhz to nyquist 2.20 3.1 8 ps rms j rms - cclf pcie gen 2.1, 10 khz to 1.5 mhz 0.08 3.0 8 ps rms j rms - cc pcie gen 3.0 0.37 1.0 8 ps rms integrated phase noise (data clock architecture) j rms - dchf pcie gen 2.1, 1.5mhz to nyquist 2.15 4.0 8 ps rms j rms - dclf pcie gen 2.1, 10 khz to 1.5 mhz 0.06 7.5 8 ps rms j rms - dc pcie gen 3.0 0.32 1.0 8 ps rms
_____________________________________________________________________________________________________________________________ _________________ dsc557 - 05 page 3 dsc557 - 0 5 crystal - less four output pcie clock g enerator absolute maximum ratings solder reflow profile item min max unit condition supply voltage - 0.3 +4.0 v input voltage - 0.3 v dd +0.3 v junction temp - +150 c storage temp - 55 +150 c soldering temp - +260 c 40sec max. esd hbm mm cdm - 4000 400 1500 v 20 qfn msl 1 @ 260 c refer to jstd - 020c ramp - up rate (200 c to peak temp) 3 c/sec max. preheat time 150 c to 200 c 60 - 180 sec time maintained above 217 c 60 - 150 sec peak temperature 255 - 260 c time within 5 c of actual peak 20 - 40 sec ramp - down rate 6 c/sec max. time 25 c to peak temperature 8 min max. 60 - 150 sec 20 - 40 sec 60 - 180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 3c/sec max. 60 - 150 sec 20 - 40 sec 60 - 180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 60 - 150 sec 20 - 40 sec 60 - 180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 3c/sec max.
_____________________________________________________________________________________________________________________________ _________________ dsc557 - 05 page 4 dsc557 - 0 5 crystal - less four output pcie clock g enerator pin description ( 20 qfn ) pin no. pin name pin type description 1 oe1 i output enable ; active high 2 nc na leave unconnected or grounded 3 vss power ground 4 vss power ground 5 clk 0 - o c omplement output of differential pair 6 clk 0+ o t rue output of differential pair 7 clk 1 - o c omplement output of differential pair 8 clk 1+ o t rue output of differential pair 9 vdd power power supply 10 nc na leave unconnected or grounded 11 oe2 i output enable ; active high 12 nc na leave unconnected or grounded 13 vss power ground 14 vss power ground 15 clk 2 - o c omplement output of differential pair 16 clk 2+ o t rue output of differential pair 17 clk 3 - o c omplement output of differential pair 18 clk 3+ o t rue output of differential pair 19 vdd power power supply 20 nc na leave unconnected or grounded pin diagram ( 20 qfn ) connection diagram (20 qfn four hcsl outputs) 1 2 3 4 5 6 7 8 9 1 0 1 8 1 9 2 0 1 5 1 6 1 7 o e 2 n c v s s v s s 1 1 1 2 1 3 1 4 v s s v s s o e 1 n c c l k 0 - 2 0 q f n 5 . 0 x 3 . 2 m m c l k 0 + c l k 1 - c l k 1 + v d d n c n c v d d c l k 3 + c l k 3 - c l k 2 + c l k 2 -
_____________________________________________________________________________________________________________________________ _________________ dsc557 - 05 page 5 dsc557 - 0 5 crystal - less four output pcie clock g enerator oe function and output waveform: hcsl ordering information dsc557 - 05 packing t: tape & reel 4 4 k package k : 20 qfn temp range e: - 20 to 70 i: - 40 to 85 l: - 40 to 105 stability 0: 100ppm 1: 50ppm 0 t clk 2 output format 1: lvcmos 2: lvpecl 3: lvds 4: hcsl 4 4 4 4 4 4 4 4 i clk 3 output format 1: lvcmos 2: lvpecl 3: lvds 4: hcsl clk 1 output format 1: lvcmos 2: lvpecl 3: lvds 4: hcsl t clk 0 output format 1: lvcmos 2: lvpecl 3: lvds 4: hcsl c l k + c l k - o e 8 0 % 5 0 % 2 0 % t r t f 1 / f 0 6 7 5 m v v i l v i h t d a t e n o e 1 o e 2 c l k 0 c l k 1 c l k 2 c l k 3 0 0 h i - z h i - z h i - z h i - z 0 1 h i - z e n e n h i - z 1 0 e n h i - z h i - z e n 1 1 e n e n e n e n c l k 1 / c l k 2 s y n c h r o n o u s c l k 0 / c l k 3 s y n c h r o n o u s
_____________________________________________________________________________________________________________________________ _________________ dsc557 - 05 page 6 dsc557 - 0 5 crystal - less four output pcie clock g enerator p ackage dimensions 20 qfn , 5.0 x 3.2 mm top view units: mm[inches] bottom view units: mm[inches]
_____________________________________________________________________________________________________________________________ _________________ dsc557 - 05 page 7 dsc557 - 0 5 crystal - less four output pcie clock g enerator side view units: mm[inches] recommended solder pad layout units: mm[inches] *connect the center pad to vss for best thermal performance disclaimer: micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in micrel s terms and conditions of sale for such products, micrel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of micrel products including liability or warranties relating to fitness for a pa rticular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right . micrel products are not designed or authorized for use as components in life support appliances, devices or systems where mal function of a pr oduct can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are inte nded for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably ex pected to result in a significant injury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or systems is a purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting fro m such use or sale. micrel , inc. 2180 fortune drive , san jose, california 95131 usa phone: +1 (408) 944 - 0800 fax: +1 (408) 474 - 1000 email: hbwhelp @ micrel .com www.micrel.com
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